Heat spreader hole pin 1 identifier

ABSTRACT

A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention relates to the fabrication of integrated circuitdevices, and more particularly, to providing an opening that facilitatesFlex Enhanced BGA (FEBGA) and Enhanced BGA (EBGA) device verificationthus improving ease of device handling and reducing errors that areintroduced by incorrect handling of FEBGA/EBGA devices.

[0003] (2) Description of the Prior Art

[0004] The creation of semiconductor devices does not only require theapplication of complex technologies with complex processing conditionsand sequences but further requires methods of packaging thesemiconductor devices once the devices have been created. Due toincreased device density and increased device complexity, input/outputcapabilities of semiconductor devices may become a device performanceconstraint and therefore place increased requirements on the packagingof semiconductor devices. Semiconductor device packages are known undera number of names and abbreviations and include laminated Ball GridArray (BGA) devices that have over time evolved from lead frame packagessuch as the Dual In Line (DIL) and Quad Flat Package (QFP). BGA packageshave shown to provide significant advantages that become especiallyimportant when the BGA approach is used to package an integrated circuitor die that has a high input/output pin count or where the semiconductordie is used in high-frequency applications. BGA packages can in additionbe mounted using conventional surface mount and assembly techniques whenthese packages are mounted on a conventional Printed Circuit Board(PCB). The mounting of a semiconductor device typically requires thedevice, a substrate on which the device is to be mounted (such as aPrinted Circuit Board), a method of connecting the die to the underlyingsubstrate, which is typically referred to as first level interconnectand for which methods of wire bonding or Tape Automated Bond (TAB) orControlled Collapse Chip Connection (C4) can be used, a method ofconnecting the substrate of the device to printed circuit cards orboards, also referred to as second level of interconnect that usesexternal metal pins or solder balls. Substrates typically containceramic or plastic materials, while semiconductor die can beencapsulated for reasons of protection whereby this encapsulation alsoencloses the first level of interconnect.

[0005] Surface mounted, high pin count integrated circuit packages havein the past been configured using Quad Flat Packs (QFP's) with variouspin configurations. These packages have closely spaced leads for makingelectrical connections distributed along the four edges of the flatpackage. These packages have become limited by being confined to theedges of the flat package even though the pin to pin spacing is small.To address this limitation, a new package, the Ball Grid Array (BGA)package, is increasingly used. This package is less confined in its I/Opin distribution because the electrical I/O contact points aredistributed over the entire bottom surface of the package. More contactpoints can thus be located on the bottom of the package, with spacingbetween the contact points that is larger than the spacing that istypically found in QFP's. These contacts are solder balls thatfacilitate flow soldering of the package onto a printed circuit board.

[0006] A Ball Grid Array (BGA) is an array of solderable balls placed ona chip carrier. The balls contact a printed circuit board in an arrayconfiguration where, after reheat, the balls connect the chip to theprinted circuit board. BGA's are known with 40, 50 and 60 mil spacingsin regular and staggered array patterns.

[0007] The packaging arrangements that are typically used for thepackaging of semiconductor devices employ a number of differentapproaches whereby these approaches can be distinguished between methodsof providing a (rigid or flexible) support structure on which thesemiconductor device is mounted with interconnect lines provided on thesurface of the support structure, methods of providing a chip-on-surfacemounting technique whereby the supporting structure can containlaminated layers of interconnect lines that are used in combination withinterconnect lines on the surface of the supporting structure andmethods of providing laminated packages that use cavities for themounting of the semiconductor devices. Where possible, the methods ofpackaging are designed such that automated packaging processes can beused for obvious reasons of costs incurred as part of the packagingprocess. In this respect, the supporting structure that uses a cavityfor the mounting of the semiconductor device does not lend itself toautomatic packaging processes since, for the various packagingapproaches that have been highlighted, the semiconductor device must,after it has been packaged, as yet be encapsulated, which is aprocessing step that cannot readily be monitored using cavity basedsupporting structures.

[0008] For the typical mounting of a chip on the surface of a laminatedsubstrate, whereby the substrate can be either ceramic (making thesubstrate rigid) or can contain an organic or plastic material (makingthe substrate flexible), electrical interconnect lines are formed in thelaminated layers of the substrate using conventional methods of metaldeposition and patterning that apply standard photolithographic methodsand procedures. The various layer of the laminated substrate areinsulated from each other using dielectric materials such as a polyimidethat can be used to separate for instance metal power and ground planesin the substrate. Electrical connections between the layers of thelaminated substrate are formed by conductive vias, the opening of thevia is, after this opening has been formed, filled with a conductivematerial in order to establish the electrically conductive paths betweenthe various layers. After the required interconnect patterns have inthis manner been established in the laminated substrate, thesemiconductor chip is positioned on the surface of the substrate andattached to the substrate by a suitable die attach material such asepoxy. This layer of epoxy serves not only to hold the semiconductor diein place but also serves as a heat transfer medium between the die andthe substrate. The top surface of the semiconductor die is connected(wire bonded) to the conductive traces on the surface of the substrate,after which the die including the bonded wires can be encapsulated.Electrical interconnects must then be established between the substrate(to which the die is at this time connected) and the surroundingelectrical circuits to which the substrate is connected. Electricaltraces are also provided in the lower surface of the substrate, a soldermask is deposited over the bottom surface of the substrate, contactballs are positioned in alignment with the contact points in the lowersurface of the substrate and re-flowed, connecting the contact ballswith the electrical traces in the bottom surface of the substrate andcompleting the interconnects between the (surface mounted) semiconductordie and the contact balls of the supporting substrate. The methoddescribed above is a method of connecting a semiconductor device usingwire bond techniques. In addition and as a substitute to the wire bondtechniques, known connection techniques in the art such as flip-chiptechniques can be applied to interconnect the semiconductor die.

[0009] Another important consideration in designing semiconductorpackages is the aspect of heat dissipation, an aspect that becomes evenmore important for devices that operate at high operating speeds or athigh levels of voltage. For the purpose of heat dissipation, asemiconductor device can be mounted on a heat sink whereby the heatdissipation can be enhanced by providing a low thermal resistivity pathbetween the semiconductor device and the heat sink. Methods that areapplied to conduct heat from the die to the heat sink and from the heatsink to the environment for further dissipation are well know in theart.

[0010] For all of the above indicated aspects of semiconductor devicepackaging and for other aspects that may not have been enumerated above,it is important that in a high speed, high throughput manufacturingenvironment semiconductor devices can be readily identified with respectto die surface and how, as a consequence, the device must be mounted infor instance a heat sink. Lack of fast and correct identification leadsto misplaced and incorrectly placed devices, resulting in increasedproduction costs. A method must therefore be provided that assures fastand correct identification of device surfaces, the method of theinvention addresses this problem of device identification.

[0011] U.S. Pat. No. 5,895,967 (Stearns et al.) shows a BGA with astiffener and spreader.

[0012] U.S. Pat. No. 5,977,626 (Wang et al.) teaches a heat spreader fora BGA.

[0013] U.S. Pat. No. 5,768,774 (Wilson et al.) shows a BGA package witha heat sink. However, this reference differs from the invention.

[0014] U.S. Pat. No. 6,011,304 (Mertol) shows a stiffer ring attachmentp3 le and removable snap in heat spreader lid.

SUMMARY OF THE INVENTION

[0015] A principle objective of the invention is to provide a methodthat allows for easy and dependable identification of semiconductordevice orientation.

[0016] Another objective of the invention is to prevent errors that areintroduced due to incorrect device surface or orientationidentification.

[0017] Yet another objective of the invention is to provide a methodthat simplifies the verification of semiconductor devices in a highspeed, high throughput semiconductor manufacturing environment.

[0018] A still further objective of the invention is to provide a methodof semiconductor device identification that has no negative effect ondevice throughput.

[0019] A still further objective of the invention is to provide a methodof device identification that applies to both small and large devicesand that is independent of the device I/O count.

[0020] In accordance with the objectives of the invention a new methodis provided to identify semiconductor devices. Prior Art methods ofdevice identification use a cutout on one side of the device or achamfer (removed corner) of the device for this purpose. This method runinto problems where packages with high I/O pin count are required sincethe space that is required for the chamfer may interfere with or limitthe number of I/O pins that can be provided on the bottom of thepackage. For this reason, the invention provides for a shallowdepression or hole on the backside of the heat sink of the package. Thisshallow depression can be used for visual and optical inspection of thedevice orientation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 shows a top view of an FEBGA/EBGA heat sink/stiffener thatis presently used whereby the Pin ID location of the invention ishighlighted.

[0022]FIG. 2 shows a top view of the ball side of a Prior Art FEBGA/EBGAdevice, highlighted in this view are the package ID markings, asfollows:

[0023]FIG. 2a uses a copper trace for the device marker

[0024]FIG. 2b uses a chamfer for the device marker.

[0025]FIG. 3 shows a number of Prior Art markings that are typicallyprovided on the ball side of the device, as follows:

[0026]FIG. 3a shows the backside view of the device, that is the side ofthe device that is opposite to the side of the device to which thecontact balls are attached, the shallow depression of the invention isapplied to this side of the device; device identification markings aretypically applied to this side of a FEBGA/EBGA device

[0027]FIG. 3b shows the ball side of the FEBGA/EBGA device of theinvention whereby this side is provided with a conventional identifiermark

[0028]FIGS. 3c through 3 g shows different conventional marks that canbe applied to the ball side of a FEBGA/EBGA device.

[0029]FIG. 4 shows a sequence of operations that is applied for thecreation of a FEBGA/EBGA device whereby the identification mark of theinvention is applied.

[0030]FIG. 5 shows a cross section of the FEBGA/EBGA heat sink with itsadjacent components-whereby the mark of the invention is provided in theheat sink.

[0031]FIG. 6 shows a top view of the conventional chamfer provided inthe heat sink of the FEBGA/EBGA device, as follows:

[0032]FIG. 6a shows a view of the conventional the chamfer and thecontact ball that is closest to the chamfer.

[0033]FIG. 6b shows a top view of the FEBGA/EBGA device looking at theFEBGA/EBGA device from the ball side of the device, a full complement ofBGA contact balls is shown in FIG. 6b.

[0034]FIG. 7 shows three cross section of BGA devices that highlight theindentation or depression of the invention, as follows:

[0035]FIG. 7a is a cross section of a FEBGA device where the device ismounted on the surface of a heat spreader,

[0036]FIG. 7b is a cross section of a FEBGA device where the device ismounted in a cavity in a heat spreader, and

[0037]FIG. 7c is a cross section of a EBGA device where the device ismounted on the surface of a heat spreader.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Referring now specifically to FIG. 1, there is shown a top viewof an FEBGA/EBGA heat sink/stiffener 10 as it is presently used wherebyhowever the Pin ID location 12 of the invention is highlighted. It mustbe emphasized that the view of the heat sink 10 that is shown in FIG. 1is the view of the side of the heat sink that is opposite to the side towhich the contact balls of the FEBGA/EBGA device will be attached.

[0039] Further shown in FIG. 1 are a number of sub-features of the heatsink as follow:

[0040]14 are alignment openings that are used to align an individualheat sink during product assembly

[0041]16 are alignment openings that are used for alignment of anassemblage of heat sinks before these heat sinks are processed asindividual heat sinks

[0042]18 are tension relieve slots that surround the body of the heatsink and that are meant to allow tension free and warpage freeprocessing and separation of the heat sinks, and

[0043]20 are inter-heat sink slots that separate individual heat sinksand that in essence also provide tension relieve between adjacent heatsinks during the process of singulation of the heat sinks.

[0044]FIG. 2 shows the FEBGA/EBGA device identification method that ispresently used. With identification is meant the step of identifyingwhich side of the FEBGA/EBGA device is facing upwards, thisidentification is a manual process even though the identification canalso be performed using for instance optical methods.

[0045]FIG. 2a uses a trace or line 22 that is provided in the surface ofthe (copper) heat sink to identify the position of the FEBGA/EBGAdevice. The location of the die 24 is highlighted, this die is mountedon the side that is shown in top view in FIG. 2a since the view of FIG.2a is the ball side of the FEBGA/EBGA heatsink.

[0046] By using the copper trace 22 it is difficult to perform positiveidentification of which side of the FEBGA/EBGA is facing upwards sinceonly after having located and after observing the copper trace can themethod of identification be assured which side of the FEBGA/EBGA isbeing observed. Contact balls 26 have been highlighted for reasons ofclarity.

[0047]FIG. 2b shows the present method of FEBGA/EBGA deviceidentification by using a chamfer 25 that is provided in one of thecorners of the FEBGA/EBGA heat sink. The problem that is encounteredwith the method of using a chamfer as FEBGA/EBGA device identificationis that the usefulness of this method is device size dependent. TheFEBGA/EBGA device is, as previously pointed out, used to increase deviceI/O count which means that a relatively large number of contact ballsare distributed over the surface of the heat sink. This in turn meansthat any reduction in the size of the surface area of the FEBGA/EBGAdevice heat sink potentially effects the number of contact balls thatcan be used which is, from a FEBGA/EBGA device design standpoint, notacceptable. This results, for FEBGA/EBGA packages other than 27×27 mmpackages, in a very small chamfer since again the chamfer surface areawould limit the number of balls that can be applied for FEBGA/EBGApackages such as 31×31 mm, 35×35 mm, 40×40 mm up through 45×45 mmpackages. In short: the approach that uses a chamfer for deviceidentification is package-size dependent and is therefore not anapproach that can be universally applied. This is further detailed underFIG. 6 below.

[0048]FIG. 3a shows the location where the mark of the invention isapplied, FIGS. 3b through 3 g show a number of conventional markingswith their location that can be applied to the ball side of thesubstrate that is used for the marking of the invention.

[0049]FIG. 3a shows a view of the side that is opposite of the ball sideof the device of a FEBGA/EBGA heat sink of the invention. The top sideof the heat sink is the side on which the semiconductor device will bemounted, the bottom side of the heat sink by contrast is the side thatis shown in FIG. 3a. The hole identifier 12 of the invention is not anopening that penetrates the heat sink but can be a depression in thesurface of the heat sink. The opposite or ball side of the heat sinkthat is shown in FIG. 3a contains a heat sink identifier that consistsof a geometric figure, several examples of the shape of this geometricfigure that can be used for the heat sink identifier are shown in thefollowing FIG. 3b through 3 f. This heat sink identifier is used notonly to identify a particular side (surface) of the heat sink but alsoidentifies the heat sink by type implying heat sink size, heatdissemination capabilities, material used for the heat sink (typicallycopper) and the like.

[0050]FIG. 3b shows the location 28 where the heat sink identifier istypically attached. FIG. 3b is a view of the ball side (the device side)of the heat sink.

[0051]FIG. 3c shows a triangular heat sink identifier 30.

[0052]FIG. 3d shows a circular (closed circle) heat sink identifier 32.

[0053]FIG. 3e shows a circular (open circle) heat sink identifier 34.

[0054]FIG. 3f shows a circular (closed circle) heat sink identifier 36combined with a square heat sink identifier 38.

[0055]FIG. 3g shows a cross shaped heat sink identifier 40.

[0056] It is clear that the geometric shape of the heat sink identifiercan take any known shape, a limitation might be that this identifier isreadily recognized by optical means. This for automatic identificationof the heat sink.

[0057]FIG. 4 shows a sequence of operations that are applied for thecreation of a FEBGA/EBGA device whereby the identification mark of theinvention is applied.

[0058] The process starts, FIG. 4, step 42, with the attachment of aheat sink for an individual FEBGA/EBGA device to the underlyingFEBGA/EBGA device substrate. The heat sink and substrate are typicallyobtained by punching (removing) the heat sink/substrate from a strip ofheat sinks/substrates.

[0059] The FEBGA/EBGA device is next (FIG. 4, step 44) attached usingconventional methods to the substrate, using for instance an adhesiveepoxy that further facilitates heat flow from the die to the underlyingheat sink.

[0060] The device is then wire bonded to the contact pads that areprovided in the surface of the substrate, thereby electricallyconnecting the FEBGA/EBGA device to the substrate, FIG. 4, step 46.

[0061] The die is encapsulated, FIG. 4, step 48. FEBGA/EBGA devicemarkings are then provided to the package on the reverse side of thepackage, that is the side where the shallow identifier of the inventionhas been provided in the heatsink, FIG. 4, step 50.

[0062] The partially completed package is next provided with BGA contactballs, FIG. 4, step 52, which are attached on the solder mask and theunderlying layer of copper interconnect lines.

[0063] As a final step the FEBGA/EBGA is optically inspected, FIG. 4,step 54.

[0064]FIG. 5 shows a cross section of the substrate and heat sink thatare used for the packaging of FEBGA/EBGA devices. Highlighted in FIG. 5are:

[0065]56, the FEBGA/EBGA device laminated substrate

[0066]58, the copper heat sink

[0067]59, a layer of epoxy that is coated on the surface of the heatsink 58

[0068]60, a layer of adhesive that is applied for the attachment of theFEBGA/EBGA device to the heat sink

[0069]62, a layer of adhesive that is applied for the attachment of theoverlying layer of copper traces

[0070]64, copper traces to which the FEBGA/EBGA device is connected

[0071]66, a solder mask that is applied for the attachment of the BGAcontact balls

[0072]68, the conventional identification mark that has been applied tothe substrate, and

[0073]70, the hole identifier of the invention.

[0074]FIG. 6 shows a top view of the conventional chamfer 72 provided inthe substrate of a FEBGA/EBGA device, as follows:

[0075]FIG. 6a shows a view of the conventional the chamfer 72 and thecontact ball 74 that is closest to the chamfer 72. The dimensions thathave been highlighted in FIG. 6a are for a typical chamfer/contact ballarrangement and are as follows:

[0076] dimension 76=0.150 mm

[0077] dimension 78=0.150 mm.

[0078] dimension 80 varies and is dependent on package size, as follows:for a 27×27 package 80=0.2000 mm and as yet allows for the use of thechamfer 72. For FEBGA/EBGA device packages of increased size, from 31×31mm up through 45×45 mm, the value of 80 decreases from 0.102 mm to 0.117mm, leaving not enough room for a chamfer to be applied, or, if achamfer were to be applied, the chamfer would be so small as to have nopractical value for inspection purposes

[0079] dimension 82 varies and is dependent on package size, as follows:for a 27×27 package 82=0.908 mm and as yet allows for the use of thechamfer 72. For FEBGA/EBGA device packages of increased size, from 31×31mm up through 45×45 mm, the value of 82 decreases from 0.144 mm to 0.165mm leaving not enough room for a chamfer to be applied, or, if a chamferwere to be applied, the chamfer would be so small as to have nopractical value for inspection purposes.

[0080]FIG. 6b shows a top view of the FEBGA/EBGA device looking at theFEBGA/EBGA device from the ball side of the device, a full complement ofBGA contact balls is shown in FIG. 6a.

[0081] Referring now to FIG. 7a, there is shown a cross section of aFEBGA device where the device 83 is mounted on the surface of a heatspreader 80. The flex tape 81 provides the mechanical and electricalinterface between the heat sink 80 and the device 83 with the contactballs 82. The device 83 is encapsulated in a plastic molding compound84. Of key importance to the invention is the indentation or depression85 that serves the previously highlight purpose of facilitating deviceorientation. FIG. 7b shows a cross section whereby the FEBGA device 83is mounted in a cavity that has for this purpose been provided in theheat sink 80. Device 83 is again surrounded by a plastic basedencapsulant 84, bond wires 86 provide electrical contact between thedevice 83 and metal traces in the flex tape 81. The identificationindentation or depression 85 is shown in the location where it isprovided in accordance with the process of the invention.

[0082]FIG. 7c is a cross section of a EBGA device 83 where the device ismounted on the surface of a heat spreader. Layer 88 is a layer of epoxythat from the interface between the substrate 87 and the heat sink 80.The orientation indentation or depression 85 is again shown in thelocation where it is affixed under the process of the invention.

[0083] Although the invention has been described and illustrated withreference to specific illustrative embodiments thereof, it is notintended that the invention be limited to those illustrativeembodiments. Those skilled in the art will recognize that variations andmodifications can be made without departing from the spirit of theinvention. It is therefore intended to include within the invention allsuch variations and modifications which fall within the scope of theappended claims and equivalents thereof.

What is claimed is:
 1. A ball grid array assembly having a metalheatsink, the ball grid array assembly comprising: a square orrectangular shaped heat sink having a thickness whereby said heat sinkfurther has a die attach surface in addition to having a marking surfacewhereby heat sink identification data is typically provided on saidmarking surface of said heat sink; and an indentation provided in saidmarking surface whereby said indentation is used to determineorientation of said BGA array assembly.
 2. The assembly of claim 1wherein an indentation has been provided in said marking surface of saidsquare or rectangular shaped heat sink whereby said indentation ispreferably located at one or more corners of said square or rectangularshaped heat sink whereby said indentation is a removal of said heat sinkmaterial that penetrates said heat sink to a depth of between about 30and 70% of the thickness of said square or rectangular shaped heat sink.3. The assembly of claim 1 wherein said ball grid array assembly ispreferably used for Flex Enhanced BGA (FEBGA) or Enhanced BGA (EBGA)devices.
 4. The assembly of claim 1 wherein said die attach surface ofsaid heatsink and said marking surface of said heatsink have been blackoxide plated.
 5. The assembly of claim 1 wherein said a square orrectangular shaped heat sink contains copper.
 6. A method of assemblinga ball grid array assembly having a metal heatsink, comprising the stepsof: providing a square or rectangular shaped metal heat sink in additionto providing a square or rectangular shaped laminate substrate wherebysaid metal heat sink and said laminate substrate are aimed at packagingball grid array devices whereby further said heat sink has a laminatesubstrate attach surface and a heat sink marking surface whereby furthersaid laminate substrate has a heat sink attach surface and a die attachsurface; applying a layer of epoxy coat to said marking surface of saidheat sink; applying a first layer of adhesive to said heat sink attachsurface of said laminated substrate; attaching said heat sink to saidlaminate substrate by overlying said heat sink over said first layer ofadhesive; applying a second layer of adhesive to die attach surface ofsaid laminate substrate; providing a layer of interconnect tracings oversaid second layer of adhesive that has been applied to said laminatesubstrate said interconnect tracings having been provided with contactpads; providing a solder mask over said layer of interconnect tracings;inserting contact balls within said solder mask such that said solderballs overlay contact pads in said layer of interconnect tracings;electrically connecting said contact balls with said contact pads insaid layer of interconnect tracings by reflow of said contact balls;encapsulating said ball grid array assembly thereby protecting said ballgrid array assembly form environmental damage; providing identificationmarkings on said marking surface of said heat sink; and performinginspection of said ball grid array assembly.
 7. The method if claim 6wherein one or more laminate substrate identification marks have beenprovided overlying said layer of second adhesive coating whereby saidlaminate substrate identification marks are facing away from said squareor rectangular shaped laminate substrate and are provided along aperiphery of said layer of second adhesive coating preferably in one ormore corners of said layer of second adhesive coating where said layerof second adhesive coating overlays said square or rectangular shapedlaminate substrate.
 8. The method of claim 6 wherein a indentation hasbeen provided in said marking surface of said square or rectangularshaped heat sink whereby said indentation is preferably located at oneor more corners of said square or rectangular shaped heat sink wherebysaid indentation is a removal of said heat sink material that penetratessaid heat sink to a depth of between about 30 and 70% of the thicknessof said square or rectangular shaped heat sink.
 9. The method of claim 6wherein said ball grid array assembly is preferably used for FlexEnhanced BGA (FEBGA) or Enhanced BGA (EBGA) devices.
 10. The method ofclaim 6 wherein said heat sink attach surface of said heatsink and saidmarking surface of said heatsink have been black oxide plated.
 11. Themethod of claim 6 wherein said a square or rectangular shaped heat sinkcontains copper.
 12. The method of claim 6 wherein said layer ofinterconnect tracings over said second layer of adhesive that has beenapplied to said laminate substrate contain copper.